In recent years "chip carriers" have emerged as a promising high-volume device packaging technique. In one simple form a chip carrier is a substantially square, relatively thin, plastic article having a cavity with bonding pads therein which are connected by a plurality of electrically conductive paths that extend through walls thereof, along the side walls, and terminate on the underside of the carrier. The conductive paths may be metallic wire leads or they may be electroplated thereon, the former is referred to as a "leaded" while the latter has been termed a "leadless" chip carrier. A semiconductor circuit chip is placed in the cavity, electrically connected to the bonding pads, and a cover placed over the cavity which may be used to hermetically seal the chip therein.
The chip carrier may be soldered to an electrically conductive land area array on the surface of a Printed Circuit Board (PCB), a metallized ceramic substrate or the like. Solder paste is screen printed on the land area array and then reflowed to form a bonded solder coating on each land area in the array. The leads on the underside of the chip carrier are then placed in mated contact with the solder coated land areas and the solder reflowed to effect a bond therebetween. Condensation soldering, various belt furnaces and hot gas apparatus have proven effective for soldering the chip carriers to the conductive land areas arrays.
It has been found necessary to maintain a gap of at least 0.010 inch between the bottom surface of the chip carrier and the PCB or other substrate surface to provide for efficient and complete flux removal and for the subsequent application of encapsulant under the carrier to protect conductors, crossovers, etc. When leaded chip carriers are used such a distance is simply obtained due to the wire lead itself which is bent about, and slightly spaced from the bottom surface of the carrier. However, use of the leadless chip carrier presents a problem due to the fact that the plated leads (e.g., gold plated over nickel) are extremely thin (e.g., 0.0016 inch) and provide substantially no spacing between the bottom of the chip carrier and the substrate.
Accordingly, the gap between the bottom surface of the leadless chip carrier and the substrate surface is governed by the height of the solder coating bonded on the land areas. Thus, the gap can be increased by increasing the height of the solder coating. System designs wherein leadless chip carriers would be soldered directly to the substrates introduce two additional reasons for maximizing the height of the solder coating. First, the solder bonding the land areas to the chip carrier leads become the compliant member which must withstand the stresses induced by the mismatch of the coefficients of thermal expansion between the chip carrier material and the substrate material. Secondly, the solder joint must accommodate the stresses caused by flexing of the PWB during manufacture or by the insertion of boards into cardguides and connectors of equipment enclosures.
One technique that has been suggested to increase the height of the solder on the land area is to dispense or stencil print very thick layers thereon and then reflow the paste to bond a thick blob of solder thereto. However, problems arise when the solder paste reflows for its height substantially decreases and the solder laterally disperses, undesirably resulting in solder bridges or shorts.
Accordingly, there is a need for a technique for increasing the height of the solder which is bonded to land areas of metallized substrate.